片上光互连作为片上互连新技术，业已成为突破电互连瓶颈的优选方案之一。随着片上光互连技术的研究与发展，片上光网络对温度准确监测，进而降低热损耗提高光功率有效利用率，逐渐成为光互连方案需要解决的一大难题。一般的片上光互连网络设计是将电互连网络替换，用光子实现信息交互，基于传统电互连温度检测方法，加入监测传感器实现片上温度监测。然而，温度对片上光网络的影响更为突出，光功率损失随温度增大而增大，使得片上光网络很难发挥出应有的传输优势。同时，加入硬件电路会使集成芯片额外增加热量。因此，迫切需要研究新的片上光网络温度实时监测方法及对片上光网络光功率损耗进行优化，进而提升片上光网络传输性能。本文基于基本光学器件微环谐振器，研究片上光网络温度检测方案，同时提出光功率损耗优化方法。

首先，在分析片上光网络传输过程的基础上，针对温度对片上光网络性能影响机制问题，搭建波长热相关微环谐振器功率损耗模型。通过搭建集群光网络模型，在模拟热点温度分布下实现光信号传输仿真。基于各微环谐振器输出光功率损耗的深度分析，构建温度分布下微环谐振器功率损耗数值模型。在300K和340K环境温度下仿真结果表明，最小绝对误差仅为0.0029dB，平均误差仅为0.0043dB。

然后，针对片上光网络温度软件检测问题，在波长热相关微环谐振器功率损耗模型的基础上，建立片上光网络温度检测模型。通过光链路数据传输路径计算各个光路由器温度。针对功耗方程组不满秩而无解的问题，基于深度优先搜索算法，运用辅助路径构建算法，通过直线型和环型两种传输链路模型构建足够的辅助路径，使问题可解。实验结果表明，针对4Í4网络，功率损耗获取与理论差异0.073~0.273dB，温度检测模型在300K~380K范围检测平均误差仅为0.5106K。所提温度检测方法与现有硬件和软件手段相对比，具有速度快、精度高、开销低的特点。

其次，深入分析片上光网络光功率损耗影响因素，研究微环谐振器物理结构、热调谐器拓扑、路由选择三种方式下对光功率损耗的优化方案。通过调节不同半径微环谐振器的波导间距设计，在热点高的位置添加辅助微环光信号进行协助传播，减少光信号丢失。同时，基于温度检测结果，提出避开热点的自适应路由算法，使光信号传输实时自动避开温度较高的区域，有效降低光功率损耗。实验结果表明，论文所提出的光功率损耗优化方案，光功率损耗减少15%以上，与XY路由、奇偶路由和西向优先路由相比，分别降低了20.15%、9.25%、10.4%。

最后，针对片上光网络热、光综合仿真开发仿真平台，实现片上光网络对光信号传输的性能分析仿真、对热点温度的分布检测仿真以及对光功率损耗优化设计的仿真。搭建了微环参数可调的8Í8多处理器网络拓扑，能够随路由设计的不同改变微环结构参数。通过参数扫描和脚本编写，支持不同的拓扑和路由算法输入给仿真网络，实现热光功率损耗优化仿真。实验结果表明，所开发的热光综合仿真平台能够实现片上光网络热光性能仿真与优化验证，简化硬件设计，提升仿真效率。

As a new technology of on-chip interconnection, on-chip optical interconnection has become one of the preferred solutions to break through the bottleneck of electrical interconnection. With the development of on-chip optical interconnection technology, on-chip optical network can accurately monitor the temperature, thus reducing the thermal loss and improving the effective utilization rate of optical power, which has gradually become a big problem to be solved in optical interconnection scheme. The general design of on-chip optical interconnection network is to replace the electrical interconnection network, use photons to realize information exchange, and add monitoring sensors to realize on-chip temperature monitoring based on the traditional electric interconnection temperature detection method. However, the influence of temperature on on-chip optical network is more prominent, and the optical power loss increases with the increase of temperature, making it difficult for on-chip optical network to give full play to its due transmission advantages. At the same time, adding a hardware circuit would add extra heat to the integrated chip. Therefore, it is urgent to study a new real-time temperature monitoring method and optimize the optical power loss of on-chip optical network, so as to improve the transmission performance of on-chip optical network. In this paper, based on the basic optical device microring resonator, the temperature detection scheme of on-chip optical network is studied, and the optical power loss optimization method is proposed.

Firstly, based on the analysis of on-chip optical network transmission process, aiming at the influence mechanism of temperature on on-chip optical network performance, the power loss model of wavelength thermal dependent microring resonator was established. By building a cluster optical network model, optical signal transmission simulation is realized under the simulation of hot spot temperature distribution. Based on the depth analysis of optical power loss of each microring resonator, a nµmerical model of power loss of microring resonator under temperature distribution was established. The simulation results at 300K and 340K show that the minimµm absolute error is only 0.0029dB, and the average error is only 0.0043dB.

Secondly, aiming at the temperature detection problem of on-chip optical network by software, a temperature detection model of on-chip optical network is established based on the power loss model of wavelength thermal dependent microring resonator. Calculate the temperature of each optical router through the data transmission path of the optical link. To solve the problem that the power system has no solution without rank, an auxiliary path construction algorithm is applied based on depth-first search algorithm. Sufficient auxiliary paths are constructed through linear and circular transmission link models to make the problem solvable. The experimental results show that for 4Í4 network, the difference between power loss acquisition and theory is 0.073-0.273 dB, and the average error of temperature detection model is only 0.5106K in the range of 300K-380 K. Compared with the existing hardware and software methods, the proposed temperature detection method has the characteristics of high speed, high precision and low cost.

Then, the influence factors of optical power loss of on-chip optical network are deeply analyzed, and the optimization scheme of optical power loss under the physical structure of microring resonator, thermal tuner topology and routing selection is studied. By adjusting the waveguide spacing of microring resonators with different radii, auxiliary microring optical signals are added to assist the propagation at high hot spots to reduce optical signal loss. At the same time, based on the temperature detection results, an adaptive routing algorithm is proposed to avoid hot spots, so that the optical signal transmission can automatically avoid the high temperature area in real time, and effectively reduce the optical power loss. Experimental results show that the optical power loss optimization scheme proposed in this paper can reduce the optical power loss by more than 15%, which is 20.15%, 9.25% and 10.4% lower than XY route, parity route and west priority route, respectively.

Finally, a simulation platform is developed for the thermal and optical integrated simulation of on-chip optical network to realize the performance analysis and simulation of optical signal transmission, the distribution detection of hot spot temperature and the optimization design and simulation of optical power loss of on-chip optical network. An 8Í8 multiprocessor network topology with adjustable microloop parameters is built, which can change the structure parameters of the microloop with different routing design. Through parameter scanning and script writing, different topology and routing algorithms can be input to the simulation network to realize the optimization simulation of thermal-optical power loss. The experimental results show that the developed thermo-optic integrated simulation platform can realize the simulation and optimization of the thermo-optic performance of on-chip optical network, simplify the hardware design and improve the simulation efficiency.

[1]Sarkar, Pal S. Photonic Network-on-Chip (NoC) Architectures for the High Performance Computing Systems[C]//IEEE Applied Signal Processing Conference (ASPCON), Kolkata, India, 2018: 198-203.

[2]Kun W, Shixiong Q, Zheng C, et al. SMONoC: Optical network-on-chip using a statistical multiplexing strategy[J]. Optical Switching and Networking, 2019, 34: 1-9.

[3]Muhammad K, Ismail F B. Thermal-aware Dynamic Weighted Adaptive Routing Algorithm for 3D Network-on-Chip[J]. International Journal of Advanced Computer Science and Applications(IJACSA), 2021,12(11), 342-348

[4]Zhanshi Yao, Kaiyi Wu, Bo Xue Tan, et al. Integrated Silicon Photonic Microresonators:Emerging Technologies[J]. IEEE Journal of Selected Topics in Quantµm Electronics, 2018, 24(1):5900324(24).

[5]Zhang W, Ye Y. A Table-Free Approximate Q-Learning Based Thermal-Aware Adaptive Routing for Optical NoCs[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020: 47(6): 372-381.

[6]Yan J T. On-chip optical channel routing for signal loss minimization[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 37(8): 1654-1666.

[7]Choudhury P D, Bhadra S, De T. A brief review of protection based routing and spectrµm assignment in elastic optical networks and a novel p-cycle based protection approach for multicast traffic demands[J]. Optical Switching and Networking, 2019, 32: 67-79.

[8]Yuan J, Fu Y, Zhu R, et al. A constrained-lower-indexed-block spectrµm assignment policy in elastic optical networks[J]. Optical Switching and Networking, 2019, 33: 25-33.

[9]Nieweglowski K, Lorenz L, Lüngen S, et al. Optical coupling with flexible polymer waveguides for chip-to-chip interconnects in electronic systems[J]. Microelectronics Reliability, 2018, 84: 121-126.

[10]Karimi R, Koohi S, Tinati M, et al. A thermally-resilient all-optical network-on-chip[J]. Microelectronics Reliability, 2019, 99: 74-86.

[11]郝强宇, 王日炎, 周伶俐. 一种带有斜率补偿的片上温度检测电路[J]. 电子技术应用, 2020, 46(08): 80-85.

[12]Anand T, Makinwa K A A, Hanµmolu P K. A VCO based highly digital temperature sensor with 0.034° C/mV supply sensitivity[J]. IEEE Journal of Solid-State Circuits, 2016, 51(11): 2651-2663.

[13]Singha S, Bhowmik B B. On-chip photonic temperature sensor using micro ring resonator[C]//Fifteenth International Conference on Wireless and Optical Communications Networks (WOCN). IEEE, 2018: 1-4.

[14]Huang W, Ghosh S, Velusamy S, et al. HotSpot: A compact thermal modeling methodology for early-stage VLSI design[J]. IEEE Transactions on very large scale integration (VLSI) systems, 2006, 14(5): 501-513.

[15]Totoki T, Koibuchi M, Amano H. An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking[C]//Sixth International Symposiµm on Computing and Networking Workshops (CANDARW). IEEE, 2018: 363-369.

[16]Said M, Shalaby A, Gebali F. Thermal-aware network-on-chips: Single- and cross-layered approaches[J]. Future Generation Computer Systems, 2019, 91: 61–85.

[17]Lee Y M, Wu T H, Huang P Y, et al. NµMANA: A hybrid nµmerical and analytical thermal simulator for 3-D ICs[C]//Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2013: 1379-1384.

[18]Hu X, Xu Y, Ma J, et al. Thermal-sustainable power budgeting for dynamic threading[C]//51st ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE, 2014: 1-6.

[19]Pagani S, Chen J J, Shafique M, et al. MatEx: Efficient transient and peak temperature computation for compact thermal models[C]//Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2015: 1515-1520.

[20]Wang Y, Aouina A, Li H, et al. Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(3): 742-746.

[21]Werner S, Navaridas J, Luján M. Efficient sharing of optical resources in low-power optical networks-on-chip[J]. IEEE/OSA Journal of Optical Communications and Networking, 2017, 9(5): 364-374.

[22]Tinati M, Koohi S, Hessabi S. Low-overhead thermally resilient optical network-on-chip architecture[J]. Nano Communication Networks, 2019, 20: 31-47.

[23]Lu L, Li X, Gao W, et al. Silicon non-blocking 4× 4 optical switch chip integrated with both thermal and electro-optic tuners[J]. IEEE Photonics Journal, 2019, 11(6): 1-9.

[24]Ye Y Y, Zhang Z. A thermal-sensitive design of a 3D torus-based optical NoC architecture[C]//Integration, the VLSI Journal, 2019, 68: 22-29.

[25]Zhang W F, Ye Y Y. An Approximate Thermal-Aware Q-Routing for Optical NoCs[C]//IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, Information and Computing Systems, 2019: 22-27.

[26]Ye Y, Zhang W, Liu W. Thermal-aware design and simulation approach for optical NoCs[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, 39(10): 2384-2395.

[27]Tinati M, Koohi S, Hessabi S. Low-overhead thermally resilient optical network-on-chip architecture[J]. Nano Communication Networks, 2019: 2-9.

[28]Liu W, Wang P, Li M, et al. Quantitative modeling of thermo-optic effects in optical networks-on-chip[C]//Proceedings of the on Great Lakes Symposiµm on VLSI 2017. 2017: 263-268.

[29]Werner S, Navaridas J, Luján M. Designing low-power, low-latency networks-on-chip by optimally combining electrical and optical links[C]//IEEE International Symposiµm on High Performance Computer Architecture (HPCA). IEEE, 2017: 265-276.

[30]Liu W, Tian G, Li M. Autonomous temperature sensing for optical network-on-chip[J]. Journal of Systems Architecture, 2020, 102: 101650(27).

[31]Vale V A C, Almeida Jr R C, Power, routing, Modulation Level and Spectrµm Assignment in all-optical and elastic networks[J]. Optical Switching and Networking, 2019, 32: 14-24.

[32]Cao R, Yang Y, Gu H, et al, A Thermal-Aware Power Allocation Method for Optical Network-on-Chip[J]. IEEE Access, 2018, 6: 61176-61183.

[33]Halavar B, Pasupulety U, Talawar B. Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures[J]. Simulation Modelling Practice and Theory, 2019, 96: 101929(27).

[34]田桂宇. 基于片上光网络的自主温度感知技术研究[D]. 重庆: 重庆大学, 2020.

[35]Ye Y, Xu J, Wu X, et al. System-level modeling and analysis of thermal effects in optical networks-on-chip[J]. IEEE transactions on very large scale integration (VLSI) systems, 2012, 21(2): 292-305.

[36]Jiao F, Dong S, Yu B, et al, Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips[J]. IEEE International Symposiµm on Circuits and Systems (ISCAS), Florence, 2018: 1-9.

[37]Sharma K, Sehgal V K. Energy-efficient and sustainable communication in optical networks on chip[J]. Sustainable Computing: Informatics and Systems, 2020, 28: 100426.

[38]Dang D, Chittamuru S V R, Mahapatra R, et al. Islands of heaters: A novel thermal management framework for photonic NoCs[C]//22nd Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2017: 306-311.

[39]Chen K J, Chao C, WuA A. Thermal-Aware 3D Network-On-Chip (3D NoC) Designs: Routing Algorithms and Thermal Managements[J]. IEEE Circuits and Systems Magazine, 2015. 15(4): 45-69.

[40]Li Y W, Lakdawala H, Raychowdhury A, et al. A 1.05 V 1.6 mW 0.45° C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS[C]//IEEE International Solid-State Circuits Conference-Digest of Technical Papers. IEEE, 2009: 340-341, 341a.

[41]Anand T, Makinwa K A A, Hanµmolu P K. A VCO based highly digital temperature sensor with 0.034° C/mV supply sensitivity[J]. IEEE Journal of Solid-State Circuits, 2016, 51(11): 2651-2663.

[42]Sönmez U, Sebastiano F, Makinwa K A A. 11.4 1650µm2 thermal-diffusivity sensors with inaccuracies down to±0.75° C in 40nm CMOS[C]//IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2016: 206-217.

[43]姚康. 基于温度敏感性分析的3D Torus片上光网络功耗优化[D]. 上海: 上海交通大学, 2018.

[44]Li D, Zhou L, Lu L, et al. Optical Power Monitoring with Ultrahigh Sensitivity in Silicon Waveguides and Ring Resonators[J]. IEEE Photonics Journal, 2017, 9(5): 1-10.

[45]Deng Y, Chen Y, Zhang Y, et al. Fuzzy Dijkstra algorithm for shortest path problem under uncertain environment[J]. Applied Soft Computing, 2012, 12(3): 1231-1237.

[46]Krencker J C, Kammerer J B, Hervé Y, et al. Electro-thermal high-level modeling of integrated circuits[J]. Microelectronics Journal, 2014, 45(5): 491-499.

[47]Luo Y, Meyer M C, Jiang X, et al. A Hotspot-Pattern-Aware Routing Algorithm for Networks-on-Chip[C]//IEEE 13th International Symposiµm on Embedded Multicore/ Many-core Systems-on-Chip (MCSoC). IEEE, 2019: 229-235.

[48]Marri J, Manishankar S, Radha D, et al. Implementation and analysis of adaptive Odd-Even routing in Booksim 2.0 simulator[C]//International Conference on Communication and Electronics Systems (ICCES). IEEE, 2019: 76-83.

[49]Binkert N, Beckmann B, Black G, et al. The gem5 simulator.[C]//ACM SIGARCH Computer Architecture News, 2011, 39(2): 1-7

[50]Mosayyebzadeh A, Amiraski M M, Hessabi S. Thermal and power aware task mapping on 3D Network on Chip[J]. Computers and Electrical Engineering, 2016, 51: 157–167.

[51]Lee D, Das S, Pande P P. Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture[J]. Integration, 2019, 65: 282-292.

[52]Satish E G, Ramachandra A C. Comparative Performance Analysis of Routing Topology for NoC Architecture[J]. Lecture Notes in Electrical Engineering, 2022, 790: 431-440.

[53]Lee S C, Han T H. Q-function-based traffic-and thermal-aware adaptive routing for 3D network-on-chip[J]. Electronics, 2020, 9(3): 392-401.

[54]Arrivo L, Schon S, Wemhoff A P. Measuring the Thermal Contact Resistance Between Cu Foams and Substrates for On-Chip Cooling Applications in Data Centers[C]//International Electronic Packaging Technical Conference and Exhibition. American Society of Mechanical Engineers. 2021: V001T02A010(10).