针对传统低压差线性稳压器（Low Dropout Regulator，LDO）对电源纹波抑制能力差，导致其在便携式电子设备等领域应用受限的问题，本文设计了一款高电源抑制比的低压差线性稳压芯片，在保证低成本、低功耗的同时可为负载提供“干净”、稳定的电源电压，具有重要的理论意义和工程应用价值。

       本文通过对LDO的基本结构、工作原理和影响电源抑制比的因素进行分析，提出了高电源抑制比LDO芯片的设计方案。首先，通过将前馈纹波消除技术应用于基准电源预稳压电路，优化了带隙基准电路，有效减小了带隙基准电路的输出纹波。其次，通过将前馈纹波消除技术应用于MOS管驱动电路，并合理选取调整管的尺寸，提升了调整管的电源纹波抑制能力。又通过优化传统折叠式共源共栅运算放大器的结构，设计了高增益高电源抑制比误差放大器电路，有效减小了由误差放大器传输的电源纹波对输出电压的影响。然后为保证电路的稳定性，提出了一种适用于高电源抑制比LDO的频率补偿方案。此外，为了确保芯片的正常工作，设计了软启动、过温保护、过流保护、使能驱动等辅助电路。最终完成了高电源抑制比低压差线性稳压芯片整体电路的设计。

      基于SMIC 0.18μm BCD工艺，在Cadence中对芯片各模块及整体电路分别进行了详细的仿真分析。结果表明，在输入电压范围为3.05V~5.5V时，输出电压可稳定在2.8V，最大输出电流为300mA，在1kHz时的电源抑制比为-71.22dB。最终完成了版图设计，并通过了各项物理验证和后仿真。

      In response to the limited application of traditional LDO in portable electronic devices and other fields due to its poor ability to suppress power ripple, a low voltage differential linear regulator chip with high power supply rejection ratio is designed in this paper. It can provide a "clean" and stable power supply voltage for the load while ensuring low cost and low power consumption, and has important theoretical significance and engineering application value.

      In order to design a LDO with high power supply rejection ratio, the basic structure and working principle of LDO are analyzed firstly, and its key performance indicators are sorted out. Then, based on market demand and design indicators, the system framework of the chip is determined, and the design scheme of the chip is clarified. In order to improve the power supply rejection ratio of LDO, the transmission path of power ripple and the expression of LDO power supply rejection ratio are analyzed, and the factors affecting the power supply rejection ratio in the circuit are determined. Based on this, various measures to improve the power supply rejection ratio are proposed, and a method to improve the power supply rejection ratio using feedforward ripple elimination technology is proposed. Among them, a reference power pre stabilization circuit was designed based on feedforward ripple elimination technology. The structure of the bandgap reference circuit was optimized, and a low-pass filter was used to further filter out the high-frequency ripple of the reference voltage, effectively improving the power supply rejection ratio of the bandgap reference circuit. At the same time, a MOS transistor driver circuit was designed based on this technology, and an appropriate size pass transistor was selected to improve the power suppression performance of the pass transistor. On the basis of a foldable common source common gate operational amplifier with a common source common gate structure as differential input, the error amplifier used in this chip has been designed, greatly improving its gain and power suppression performance. To ensure the stability of the circuit, a compensation scheme for the LDO structure proposed in this paper is proposed. In addition, in order to ensure the normal operation of the chip, the soft start circuit, over temperature protection circuit, over current protection circuit, and enabling drive circuit are designed, and the automatic low power consumption mode of the chip is designed. Finally, the overall circuit design of the high power supply rejection ratio and low voltage differential linear regulator chip is completed.

     Firstly, the basic structure and working principle of LDO are analyzed in this paper, and its key performance indicators are sorted out. Combined with market demand and design indicators, the system framework of the chip is determined, and the design scheme of the chip is clarified. Secondly, in order to improve the power supply rejection ratio of LDO, the transmission path of LDO power ripple and the expression of its power supply rejection ratio are analyzed, and the influencing factors on the power supply rejection ratio in the circuit are determined. Based on this, various measures to improve the power supply rejection ratio are proposed. Among them, in order to improve the power supply rejection ratio of the bandgap reference circuit and the adjustment transistor, based on feedforward ripple elimination technology, the reference power pre-regulation circuit and MOS transistor driver circuit are designed, and low-pass filter is used to further filter out high-frequency ripple of the reference voltage. Combined with the requirements of high power rejection ratio LDO for error amplifiers, a foldable common source common gate operational amplifier with a cascode structure as differential input is selected to improve the gain and power suppression performance of the error amplifier. Then, in order to ensure the stability of the circuit, a compensation scheme for the LDO structure proposed is proposed. In addition, to ensure the normal operation of the chip, the soft start circuit, over temperature protection circuit, over current protection circuit, and enabling drive circuit are designed, and the automatic low power consumption mode of the chip is also designed. Finally, the overall circuit design of the high power supply rejection ratio and low voltage differential linear regulator chip was completed.

      Based on SMIC 0.18μm BCD process, a detailed simulation analysis of the chip circuit is conducted in Cadence. The results showed that when the input voltage range was 3.05V~5.5V, the m output voltage can be stabilized at 2.8V, the maximum output current was 300mA, and the high power supply rejection ratio at 1kHz is -71.22dB. The final layout design was completed and passed various physical verifications and post simulations.

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