随着无线移动通信技术的快速发展，无线移动通信已经逐步成为人们交流和联系的主要手段。然而由于无线传输介质的开放性使其存在很大的安全隐患。作为一种极具竞争力的无线接入技术，LTE标准制定开始就将安全问题提到一定高度。然而无线移动终端存在运算能力、存储空间和电池容量有限等问题，一些复杂的数据运算需要通过专用的硬件来加速实现。 本文基于AHB总线，研究和设计了一款用于LTE终端PDCP层中的加解密硬件加速器。论文仔细研究了LTE标准中的安全性架构协议，对加解密硬件加速器进行了结构设计和模块划分。实现了CMAC模式、CTR模式、UIA2算法、UEA2算法以及AES核和SNOW 3G核的硬件设计。在AES核的设计过程中，为了减小硬件面积，利用复合域降阶的方法，用组合逻辑电路实现了字节代换操作；采用矩阵因子分解的方法实现了列混合操作。在SNOW 3G核的设计中，S-BOX S1采用AES S-BOX的实现方式，节省了硬件资源开销。在设计加解密IP核时，加密与完整性保护模块并行处理，提高了数据处理速度的同时节约了资源。在密钥管理方案中，采用硬件提前对初始密钥进行密钥扩展运算并且存储的方式，在密钥不变的情况下，不用重新对初始密钥进行密钥扩展运算，降低了功耗。 本文使用Verilog硬件描述语言，对加解密硬件加速器进行了RTL描述。利用EDA工具对系统进行了逻辑功能仿真和静态时序分析。在基于Virtex-6的FPGA硬件平台上对系统进行了验证，验证结果表明：本设计在满足各项功能及设计目标的基础上实现了速度和资源的平衡，具有较好的速度面积比。

With the rapid development of wireless communication technology, wireless communication has gradually been the main expression and communication in human life. however, a big security risk exists because of the openness of wireless networks. As a very competitive wireless access technology, standard of LTE has taken into account security issues at the very beginning. Whereas, there are limitations for the wireless mobile terminal, such as calculating ability, storage space, battery capacity, and so on. As a result, some complex data operations need to be realized by special hardware accelerator. Based on the AHB bus, a encryption and decryption hardware accelerator used in PDCP layer of LTE communication terminal has been researched and designed in this thesis. Firstly, the security layer protocol in LTE standard was researched in detail to complete the structural design and module division of the hardware accelerator. Secondly, complete the CCM mode, CTR mode, UIA algorithm, UEA algorithm as well as the hardware design of AES and SNOW 3G. During designing the AES core, in order to reduce the hardware area, a special circuit structure is proposed to realize the ShiftRow operations. According to the composite field reduction method, combinational logic circuits are utilized to implement the SubByte operations. In the design of SNOW 3G, AES S-BOX was used by S-BOX S1 to save the sources while encryption and integrity protection module were parallel processed to improve the data processing speed and save resources in the design of encryption and decryption IP. In the key management scheme, hardware was used preliminarily in the extended algorithm and saving of the initial key, what’s more, when the key is unchanged, no extended algorithm should be performed in the initial key, for which would reduce the power. The hardware accelerator has been described in RTL level using Verilog hardware description language, and EDA was used to analyze the logic function simulation and static timing. Then the whole system was tested by FPGA hardware platform based on Virtex-6. The results showed that the speed and resource in the design were balanced on the basis of achieving the whole functions and the design objective while the design was of high speed area ratio.