针对传统低压差线性稳压器（Low Dropout Regulator, LDO）对电源纹波的抑制能力及噪声性能不足，导致其在便携式电子设备等领域应用受限的问题，本文设计了一款低噪声高电源抑制比（Power Supply Rejection Ratio, PSRR）的LDO芯片，在保证高稳定性的同时可为负载提供“干净”的电源电压，具有重要的理论意义和工程应用价值。

本文通过对基本LDO结构的工作原理及关键性能参数进行分析，提出了一种低噪声高PSRR的LDO芯片设计方案。首先，为提高LDO的噪声性能，通过加入一种改进结构的低通滤波器滤除了带隙基准电路的输出噪声，又通过采用折叠共源共栅和源极负反馈结构的运放降低了误差放大器的等效输入噪声；其次，为提高LDO的PSRR，基于前馈纹波消除技术设计了带隙基准的预稳压电路，通过设计一条前馈通路，有效降低电源电压的纹波，优化了带隙基准电路的PSRR，并将该技术应用于MOS管驱动电路，通过在电源电压与功率管栅极之间建立一条前馈通路，实现电源纹波在功率管栅端的等量复制，有效降低功率管栅源电压对电源纹波的敏感度，进一步提升LDO的PSRR；最后，为保证电路的稳定性，采用传统ESR电阻串联外接大电容的频率补偿方式实现了系统的稳定。此外，为确保芯片正常工作，设计了过温保护、过流保护、软启动及使能逻辑控制电路模块。最终完成了低噪声高PSRR的LDO芯片整体电路设计。

基于SMIC 0.18μm BCD工艺对整体电路进行仿真分析，结果表明芯片在输入电压范围为3~5.5V时，输出电压可稳定在2.8V，最大输出电流为300mA，在10Hz到100KHz频率范围内输出积分噪声为38.3μVrms，低频PSRR为89.5dB，全频带范围内PSRR均高于50dB。最后对整体电路的版图进行设计，并通过了相关物理验证及后仿真验证。

Aiming at the problem that the traditional Low Dropout Linear Regulator (LDO) has insufficient ability to suppress power ripple and noise performance, which leads to its limited application in portable electronic devices and other fields. In this paper, a LDO chip with low noise and high Power Supply Rejection Ratio (PSRR) is designed, which can provide "clean" power supply voltage for the load while ensuring high stability, which has important theoretical significance and engineering application value.

By analyzing the working principle and key performance parameters of the basic LDO structure, a design scheme of LDO chip with low noise and high PSRR is proposed in this paper. Firstly, in order to improve the noise performance of the LDO, an improved low-pass filter is added to filter the output noise of the bandgap reference circuit, and the equivalent input noise of the error amplifier is reduced by adopting the folded common-gate and negative feedback structure of the op-amp. Secondly, in order to improve the PSRR of LDO, a bandgap reference circuit with pre-regulated voltage circuit is designed based on feed-forward ripple elimination technology. By designing a feed-forward path to effectively reduce the ripple of the power supply voltage, the PSRR of the bandgap reference circuit is optimized, and this technology is also applied to the MOS drive circuit. By establishing a feed-forward path between the power supply voltage and the gate of the pass transistor , the power ripple is duplicated equally at the gate of the pass transistor , which effectively reduces the sensitivity of the pass transistor gate-source voltage to the power ripple and further improves the PSRR of the LDO. Finally, in order to ensure the stability of the circuit, the frequency compensation method of traditional ESR resistors connected in series with external large capacitors is used to realize the stability of the system. In addition, in order to ensure the normal operation of the chip, over-temperature protection, over-current protection, soft start and enable logic control circuit modules are designed. Finally, the overall circuit design of LDO chip with low noise and high PSRR is completed.

The simulation analysis of the whole circuit based on SMIC 0.18μm BCD process shows that when the input voltage range is 3~5.5V, the output voltage can be stabilized at 2.8V, the maximum output current is 300mA, and the output integral noise is 38.3μVrms in the frequency range of 10Hz to 100Hz. The low frequency PSRR is 89.5dB, and the PSRR is higher than 50dB in the full frequency band. Finally, the layout of the whole circuit is designed, and the relevant physical verification and simulation verification are passed.

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