数字产品在飞速发展，数字电视技术也在迅速的赶超时代的脚步,数字电视节目版权保护则成为数字电视越来越关键的技术。利用水印技术实现视频版权保护成为一种有效的保护手段，目前的很多保护方法都是将水印嵌入到具体视频帧中。本课题以数字电视节目版权保护与数字视频水印技术相结合为目的，采用FPGA(Field Programmable Gate Array)技术对MPEG-2（Moving Picture Experts Group）编码标准的TS流(transport stream，传输流)进行了节目信息特征的检测和视频帧的提取，为将数字视频水印嵌入到数字电视节目视频中提供了实践基础，并针对此数字电视版权保护方案提出一种机顶盒设计方案。 本文首先对数字电视广播系统原理和MPEG-2标准做了简单的介绍。重点且详细的分析了MPEG-2 TS流的数据结构，运用FPGA编程语言verilog设计功能模块来提取PAT（Program Association Table,数字电视专用信息的节目关联表）、PMT（Program Map Table，节目映射表）和PES（Packetized Elementary Streams，打包基本码流）的相关信息，并对模块功能进行了功能仿真，然后使用友晶公司的开发板DE2-115进行调试，通过signal TAP抓取信号，经过数据的对比，证明本文的方案是可行的。课题中的功能模块用verilog语言进行编辑，编译环境为QuartusII 11.0。经分析结果表明：此设计能够将数字电视节目视频TS流信息正确地提取出来。 本文还提出了一种基于FPGA的MPEG-2 TS流检测的硬件设计方案，对此硬件结构和具体功能进行了描述。对硬件芯片进行了芯片的选型说明，接口的设计以及绘制了各模块的相关的电路原理图。

With the rapid development of digital television technology, the copyright protection of digital TV has become increasingly important. Digital watermarking technology is an effective means of copyright protection of video, the existing methods are mostly the video frame of video watermark is embedded in the concrete. In order to effectively combines the digital TV program copyright protection and digital video watermark technology, the research on MPEG-2 using FPGA Technology coding standard TS were extracted detection and video frame feature and storage, This paper briefly introduced the principle of digital television broadcasting system and standard MPEG-2. The data structure of MPEG-2 TS flow are analyzed in detail, using FPGA programming language design function module to extract PAT , PMT and PES of the relevant information, and the module functional simulation, DE2-115 development board and board level debugging the use of friends of the crystal company, signal capture by signal TAP, through the data comparison, show that this scheme is feasible.The function module with Verilog language editing, the compiler environment QuartusII 11, simulation environment for the modelsim-Altera 6.6 stater Edition. The analysis results show that: the design of hand to digital TV video transport stream information correctly extracted, on the other hand can be used for real-time extraction of digital TV program corresponding video frames.This paper also presents a flow detection of FPGA MPEG-2 TS based hardware design scheme, the hardware structure and its functions are described. The chip described chip selection, interface design and the design process of each module and the related circuit diagram.