系统级芯片是当前CMOS技术发展的潮流，在片上系统(SOC)中一般会将模数转换器(ADC)和数模转换器(DAC)等与数字信号处理(DSP)模块等集成在一个芯片上。随着数字信号处理技术在高分辨率图像、视频处理及无线通信等领域的广泛应用，系统对模数转换器提出了更高的要求，对高速高精度低功耗的模数转换器的需求十分迫切。模数转换器的研究是当前的热点。 在各种模数转换器中，流水线型模数转换器由于其分级转换、流水线操作的特点，在实现较高精度的同时，仍可以保持较高的速度和较低的功耗，可以在速度、精度、功耗和芯片面积之间达到最好的折中。 本文在TSMC 0.25μm 3.3V CMOS数模混合工艺下设计了一个采样精度10bit、工作频率100MHz的低功耗流水线A/D转换器。 本设计前八级为1.5位/级流水线结构，第九级为2位FLASH结构，并使用了数字校正电路来保证转换结果的正确，达到预期的设计目标，且折中考虑了速度、功耗和动态特性的要求。在具体的电路设计中，采用了折叠式共源共栅OTA、CMOS自举采样开关、带有RS触发器的动态比较器等流行的电路技术，降低噪声、失真和失配等非理想因素；通过采用跨导运算放大器(OTA)共享技术来降低系统的功耗和面积；加入了以延迟锁相环(DLL)为核心的时钟稳定电路，保证了采样时钟的稳定性。 在Cadence环境下使用Spectre软件对流水线A/D转换器模块电路进行模拟仿真。同时利用Matlab软件对流水线A/D转换器的静态和动态参数进行了计算，并绘制了流水线A/D转换器的整体版图。

System-on-chip is the trend in current CMOS technologies, and the analog-to-digital converter (ADC), the digital-to-analog (DAC) and the DSP module are usually integrated in a single chip. With the digital signal processing technology widely applied in high resolution imaging, video processing and wireless communication, the system puts forward higher requirements for ADC, and faster, higher resolution and lower power dissipation ADCs are impending needed. The study on ADC is a current hot research topic. There exist various types of ADCs, but the pipelined ADC can do the best performance when speed, resolution, power dissipation and chip size are considered, for the partitioned nature can achieve high resolution but still remain low power dissipation. In the thesis, a 10-bit 100MHz low-power pipelined A/D converter was designed base on TSMC 0.25μm 3.3V CMOS mixed-mode process. The first eight stages used 1.5 bit/stage pipeline structure and the ninth FLASH structure in the design. Digital correction circuit was adopted to ensure the conversion result, and the rate, power consumption and dynamic characteristics were considered at the same time, and finally reached the expected goal. For the concrete circuit design, several pop circuit techniques as folded cascade OTA, CMOS bootstrapped sampling switch, and dynamic comparator with RS-trigger were used to reduce non-ideal factors like noise, distortion and mismatch. OTA sharing techniques was used to decrease the system power consumption and area. Clock duty cycle stabilizer was added to keep the stability of sampling clock. The simulation of pipeline A/D converter module by Spectre under Cadence environment was completed. The static and dynamic parameters were calculated by Matlab. The whole layout of pipeline A/D converter was given at the ending.