集成电路随着芯片规模的不断扩大已经进入了片上系统（SOC）时代，基于IP核(Intellectual Property)的设计方式是IC设计发展的必然趋势。拥有自主知识产权的IP核具有很高的通用性和灵活性，可以根据不同需求应用到各种嵌入式系统中。 本设计基于面向网络应用的SOC项目，实现了一种完全兼容MIPS 4Kc CPU的软IP核，以其为核心构建了包含存储器、串行总线接口等外设的SOC，开发了底层驱动与应用程序，并在Altera公司的开发板上通过了验证。本设计的工作涵盖了硬件和软件两个部分： 硬件方面，深入分析MIPS 4Kc体系结构，对其进行系统模块划分与Verilog代码实现。流水线采用五级流水，采用级间旁路等方式降低了由数据相关、控制相关、结构相关造成的流水线停顿延迟。采用Wallace-tree改进了乘法器，缩短了乘法运算的时间。数据、指令分别构建了容量为4KB的一级缓存，大大提高了CPU运行的效率。为扩大应用范围，设计了兼容Wishbone总线的大吞吐量总线接口控制器。SOC中集成了存储器、串行总线接口、LED和七段码显示模块。 软件方面，设计了CPU的启动代码boot-loader，初始化系统运行环境，针对设计使用的开发板Altera Stratix II DSP Development Board上的硬件资源，开发了串行总线接口等外设的底层驱动程序，并在顶层编写了一个字符回显程序用于验证系统正确性。设计完全兼容MIPS 4Kc，软件代码在Linux环境下使用GCC编译。 设计使用Modelsim SE进行了模块级验证、极限点验证，使用Quartus II+Modelsim进行了FPGA综合与时序仿真，并最终在FPGA硬件平台上完成验证。验证结果与综合报告表明，设计完全兼容MIPS 4Kc，性能达到了设计要求，在FPGA平台上可以在系统时钟为70MHz的条件下运行，且占用资源较少。 本设计最终构建了一个基本完整的SOC，涵盖了开发调试中必要的功能部件，CPU核完全兼容MIPS 4Kc，可以采用GCC作为开发环境，便于软件开发，为项目所需网络应用SOC设计工作奠定了基础。

IC is stepping into the era of SOC with the increasing of chip scale. An inevitable trend of IC design is designing based on IP. IP cores with outstanding versatility and flexibility can be applied in various embedded-systems specified by different application. This dissertation implements a soft IP core compatible with MIPS 4Kc CPU and builds a SOC that contains memory, UART and other peripherals around the core. Low-level drivers and applications are developed and verified on Altera’s development board. Researching consists of both HW part and SW part. In HW part, the core is divided into modules and implemented by Verilog based on analysis of MIPS 4Kc architecture. The pipeline has five stages. Stalls caused by relativity are avoided by bypass between stages. Multiplier is improved by using Wallace-tree structure. Instruction and data cache are both 4KB. The bus interface unit is compatible with Wishbone protocol. The SOC consists of memory, UART, LED and segment display module. In SW part, boot-loader code is written to initial the system after reset. Drivers for UART and other peripherals are developed to use HW resources on the DSP Development Board. A top application program which can perform character re-display is used to verify the system. Since the core is compatible with MIPS 4Kc, codes are compiled by GCC. The project is verified at module level and hazard case under Modelsim SE and synthesized and timing-simulated under Quartus II and Modelsim SE. Verification is completed on the hardware under Quartus II. The results of verification and reports of synthesis indicate that the design is compatible with MIPS 4Kc and has excellent performing. It can run at 70MHz without too much resource cost. This project builds an elementary SOC with essential modules in developing and debug. The CPU core is fully compatible with MIPS 4Kc, it makes software developing convenience by compiling code with GCC. In a word, it makes foundation for later SOC developing for specified requirements.