论文中文题名: | 基于VC-1视频标准的离散余弦变换实现及验证 |
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学号: | 200906211 |
保密级别: | 公开 |
学科代码: | 080903 |
学科名称: | 微电子学与固体电子学 |
学生类型: | 硕士 |
学位年度: | 2012 |
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第一导师姓名: | |
论文外文题名: | Realization and verification of Discrete Cosine Transform Based on VC-1 Video Standard |
论文中文关键词: | |
论文外文关键词: | the VC-1 video standard ; image compression ; DCT transform ; soft IP |
论文中文摘要: |
移动通信和互联网成为当今世界发展最快,前景最诱人的业务。它们的增长速度都是任何预测家未曾预料到的。在移动互联网中有海量视频需要处理、存储。因此作为移动互联网的终端例如手机对视频处理的能力要求越来越高。作为微软的高清视频标准的VC-1整合了MPEG及H.264的优点,对视频有很杰出的效能表现。
论文以基于VC-1的整数DCT(离散余弦变换)变换IP软核设计为目标,主要进行了两方面的工作:一方面是整数DCT变换的算法分析与IP软核设计;另一方面是对整数DCT变换IP软核进行FPGA验证。重点研究了8×8和4×4的整数DCT变换矩阵的结构和特点,然后推广到8×4和4×8的DCT变换,将矩阵变换中的乘法运算转换为运算单元可复用的加法运算和算术位移运算。在此基础上,分析了基于行列分离方案实现2-维整数DCT变换的硬件结构。
本文使用Verilog HDL编写了基于VC-1的整数DCT的RTL级代码,并用Cadence的NC-Verilog进行功能仿真,仿真结果验证了设计功能的正确性。最后,将2-维整数DCT IP软核在FPGA上进行了验证。论文的研究成果为进一步开发IP核库奠定了良好的基础。
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论文外文摘要: |
In recent years, mobile communications and the Internet has become the fastest-growing and the most attractive prospects businesses. Their growth rate has not been anticipated. There are massive video need to process and storage in the mobile Internet. The demand of video processing capability of the mobile Internet terminal such as mobile phone is increasing day by day. Microsoft's high-definition video standard VC-1 combines the advantages of the MPEG and H.264, has very outstanding performance.
This article is aimed to design an IP soft-core with VC-1 integer DCT (Discrete Cosine Transform). There are two aspects of work: one is the integer DCT algorithm analysis and IP soft-core design; the other is FPGA verification of the integer DCT IP core. The structure and characteristics of the 8 × 8 and 4 × 4 integer DCT matrix are studied, and then are extended to 8 × 4 and 4 × 8 DCT. The multiplication.is replaced by addition and arithmetic bit shift operator in matrix transformation. On this basis, the 2 - dimensional integer DCT transform hardware architecture based on the ranks of the separation program. The hardware structure which implements 2-dimensional integer DCT through RCM is analyzed.
The RTL code based on VC-1 integer DCT is completed with Verilog HDL and simulated by Cadence NC-Verilog simulator. The simulation results demonstrate the correctness of the design features. Finally, the 2-dimensional integer DCT IP soft core are verified in FPGA. The research results have laid a good foundation for the further development of the IP core library.
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中图分类号: | TN431.2 |
开放日期: | 2012-06-25 |