- 无标题文档
查看论文信息

论文中文题名:

 面向阵列处理器的光电混合交换机制研究与设计    

姓名:

 黄锦扬    

学号:

 20207223076    

保密级别:

 保密(1年后开放)    

论文语种:

 chi    

学科代码:

 085400    

学科名称:

 工学 - 电子信息    

学生类型:

 硕士    

学位级别:

 工程硕士    

学位年度:

 2023    

培养单位:

 西安科技大学    

院系:

 通信与信息工程学院    

专业:

 电子与通信工程    

研究方向:

 集成电路设计    

第一导师姓名:

 蒋林    

第一导师单位:

 西安科技大学    

论文提交日期:

 2023-06-19    

论文答辩日期:

 2023-06-02    

论文外文题名:

 Research and Design of Optoelectronic Hybrid Switching Mechanism for Array Processor    

论文中文关键词:

 阵列处理器 ; 光电混合互连 ; 光电路交换 ; 光分组交换 ; H树网络 ; 可重构    

论文外文关键词:

 Array processor ; Optoelectronic hybrid interconnection ; Optical circuit switching ; Optical packet switching ; H-tree network ; Reconfigurable    

论文中文摘要:

       光交换机制是片上互连通信的重要组成部分,光交换机制的选择在很大程度上影响网络的时延、吞吐等性能。然而,单一的光电路交换和光分组交换无法满足可重构阵列处理器多种应用场景下的数据传输需求。因此,论文研究并设计了面向阵列处理器的光电混合交换机制。论文主要从光电混合H树型网络研究与设计、混合交换路由开关设计与研究、簇间数据交互研究与设计和基于混合交换机制的长短记忆网络(Long Short Term Memory, LSTM)模型搭建与FPGA测试四个方面展开。

       首先,根据项目组研究的可重构阵列H树型拓扑结构,设计基于树形拓扑的光电混合H树互连网络结构。根据H树拓扑中通过交叉节点的路径数量,设计相应端口数的光电转向开关,满足信号的转向传输需求。基于OMNeT++对光网络层性能进行测试,结果表明在单播模式下簇间传输节点平均冲突率为15.6%,多播模式下簇间传输节点平均冲突率为23.9%。单播模式下,信息注入率为0.6时,本文所提出的路由结构较Corona与2D Mesh路由网络平均吞吐率分别增加了9.3%与22.6%。多播模式下,信息注入率为0.5时,本文所提出的路由网络较Corona与2D Mesh路由网络平均吞吐率分别增加了31.2%与27.3%。

其次,设计两种路由开关满足光电路交换和光分组交换数据传输需求。路由开关设计主要包括数据传输格式以及路由控制单元、混合交换单元、环回缓存单元和数据划分重组单元等电路结构。并进行光电混合路由开关FPGA测试与性能分析。结果表明,次级路由开关的LUT使用总量为828,中心节点路由开关的LUT使用量为783。在均匀模式下,信息注入率为0.6时,提出的路由结构较CDVC、ViChaR与EDVC F-R/W路由开关吞吐率分别增加了35.7%、22.5%与8.5%。在热点模式下,信息注入率为0.6时,本文所提出的路由结构较CDVC、ViChaR与EDVC F-R/W路由开关吞吐率分别增加了44.2%、15.4%与19.6%。

        然后,针对簇间多通道的数据交互网络结构,设计同时使用光电路交换(Optical Circuit Switching, OCS)和光分组交换(Optical Packet Switching, OPS)的簇间传输网络。通过设计路由策略,灵活切换光电路交换和光分组交换传输模式,并设计四端口和五端口光路由器进行光电混合传输。实验结果表明,光H树网络与同规模的片上光互连结构如λ-Router、GWOR、Light相比,各路径平均信噪比分别提高了38.5%、36.0%、17.1%。在均匀模式下,信息注入率为0.2时,本文所提出的路由结构相比动态缓存路由网络与网格型路由网络归一化吞吐率分别增加了11.2%与7.0%。在均匀模式下,信息注入率为0.3时,本文所提出的路由结构相比多通道动态缓存路由网络与网格型路由网络平均信息传输延时分别减少了5.5%与10.5%。

       最后,基于PyTorch框架搭建LSTM网络模型,通过对模型进行剪枝和量化得到瓦斯浓度预测模型参数导入到FPGA中。并设计LSTM硬件模块的激活函数计算单元、网络运算单元、门状态更新单元。基于混合交换H树路由结构实现LSTM网络运算单元,并对其进行功能测试和性能分析。实验结果表明,瓦斯浓度等级预测软硬件结果基本一致,在20次软硬件结果对比中,仅一次不同。结合混合交换H树的LSTM网络运算单元瓦斯浓度等级分类预测准确率最多提高1.21%。

论文外文摘要:

      The optical switching mechanism is an important component of on-chip interconnection communication, which greatly affects the network's performance such as latency and throughput. However, single optical circuit switching and optical packet switching cannot meet the data transmission requirements of reconfigurable array processors in various application scenarios. Therefore, the paper studies and designs an optoelectronic hybrid switching mechanism for array processors. The paper mainly focuses on four aspects: the research and design of H-tree networks based on optoelectronic hybrid switching mechanism, the design and research of hybrid switching routing switches, the research and design of inter cluster data interaction, and the construction of Long Short Term Memory networks based on hybrid switching mechanism and FPGA testing.

        Firstly, based on the reconfigurable array H-tree topology studied by the project team, a hybrid optoelectronic H-tree interconnection network architecture based on tree topology is designed. Based on OMNeT++, the performance of the optical network layer was tested, and the results showed that the average conflict rate between cluster transmission nodes in unicast mode was 15.6%, while in multicast mode, the average conflict rate between cluster transmission nodes was 23.9%. In unicast mode, when the information injection rate is 0.6, the proposed routing structure increases the average throughput of Corona and 2D Mesh routing networks by 9.3% and 22.6%, respectively. In multicast mode, when the information injection rate is 0.5, the proposed routing network has an average throughput increase of 31.2% and 27.3% compared to Corona and 2D Mesh routing networks, respectively.

       Secondly, two types of routing switches are designed to meet the data transmission requirements of optical circuit switching and optical packet switching. The design of routing switches mainly includes data transmission formats and circuit structures such as routing control units, hybrid switching units, loop back cache units, and data partitioning and reassembly units. And conduct FPGA testing and performance analysis for optoelectronic hybrid routing switches. The results show that the total LUT usage of secondary routing switches is 828, and the LUT usage of central node routing switches is 783. In uniform mode, when the information injection rate is 0.6, the proposed routing structure increases the switch throughput by 35.7%, 22.5%, and 8.5% compared to CDVC, ViChaR, and EDVC F-R/W routing, respectively. In hotspot mode, when the information injection rate is 0.6, the routing structure proposed in this paper increases the switch throughput by 44.2%, 15.4%, and 19.6% compared to CDVC, ViChaR, and EDVC F-R/W routing, respectively.

        Then, for the multi-channel data exchange network structure between clusters, design an inter cluster transmission network that uses both optical circuit switching and optical packet switching. The experimental results show that the optical H-tree network and the same scale on-chip optical interconnection structure are as follows λ-Router, GWOR, and Light, the average signal-to-noise ratio of each path has increased by 38.5%, 36.0%, and 17.1%, respectively. In uniform mode, when the information injection rate is 0.2, the proposed routing structure increases the normalized throughput by 11.2% and 7.0%, respectively, compared to dynamic cache routing networks and grid routing networks. In uniform mode, when the information injection rate is 0.3, the proposed routing structure reduces the average information transmission delay by 5.5% and 10.5%, respectively, compared to multi-channel dynamic cache routing networks and grid routing networks.

        Finally, an LSTM network model was built based on the PyTorch framework, and the parameters of the gas concentration prediction model were obtained by pruning and quantifying the model and imported into FPGA. The activation function computing unit, network computing unit and gate status updating unit of LSTM hardware module are designed. Implement LSTM network computing unit based on hybrid switching H-tree routing structure, and perform functional testing and performance analysis on it. The experimental results show that the software and hardware results of the gas concentration level prediction system are basically consistent, and only one of the 20 software and hardware results comparisons is different. The accuracy of gas concentration level prediction can be improved by up to 1.21%.

参考文献:

[1] GHARAN M and KHAN G N. Reconfigurable on-chip interconnection networks for high performance embedded SoC design [J]. Journal of Systems Architecture, 2020, 35(24): 36-41.

[2] Xiao M Y, Tseng T M, Schlichtmann U. Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs[J], IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 31(5): 124-133.

[3] ZHANG J, ZHAO M W, WANG Y. Compact configuration of wavelength-selective non-blocking photonic crystal optical router for networks-on-chip[J], Optik, 2022, 254(2): 531-539.

[4] FADHEL M, GU H X and WEI W T. DORR: A DOR-based non-blocking optical router for 3D photonic network-on-chips: regular section[J]. IEICE Transactions on Information and Systems, 2021, 104(5): 688-696.

[5] Wang F, Yao H P, Wang J J, et al. Hybrid Optical-Electrical Data Center Networking: Challenges and Solutions for Bandwidth Resource Optimization[J]. IEEE Communications Magazine, 2022, 60(11): 90-96.

[6] WANG K, QI S, CHEN Z, et al. SMONoC: Optical network-on-chip using a statistical multiplexing strategy[J]. Optical Switching and Networking, 2019, 34(1): 9-17.

[7] Xue X W, Calabretta N. Nanosecond optical switching and control system for data center networks[J]. Nature Communications, 2022, 13(1): 2257-2263.

[8] SU Y, XIE Y, SONG T, et al. A novel virtual-cluster based architecture of double-layer optical networks-on chip[J]. Journal of Lightwave Technology, 2020, 38(14): 3553-3562.

[9] LIU F Y, ZHANG H B, CHEN Y W, et al. Wavelength-reused hierarchical optical network on chip architecture for manycore processors[J]. IEEE Transactions on Sustainable Computing, 2019, 4(2): 231-244.

[10] GUO P X, HOU W G, GUO L, et al. Fault-tolerant routing mechanism in 3D optical network-on-chip based on node reuse[J]. IEEE Transactions on Parallel and Distributed Systems, 2020, 31(3): 547-564.

[11] ZHU L J, GU H X, YANG Y T, et al. Making path selection faster: a routing algorithm for ONoC[J], Opt. Express, 2021, 15(4): 10221-10235.

[12] CHENG T, WU N, YAN G, et al. Poet: a power efficient hybrid optical NoC topology for heterogeneous CPU-GPU systems[C]//IECON 2019-45th Annual Conference of the IEEE Industrial Electronics Society. IEEE, 2019: 3091-3095.

[13] Zhang T, Ren F Y, Bao J K, et al. Minimizing Coflow Completion Time in Optical Circuit Switched Networks[J]. IEEE Transactions on Parallel and Distributed Systems, 2021, 32(2): 457-469.

[14] Yu X S, Gu H X, Li S, et al. A Fast Circuit Scheduling Scheme for Optical Data Center Networks[J]. IEEE Photonics Technology Letters, 2021, 33(11): 561-564.

[15] Bibi H, Khan F Z, Ahmad M, et al. Dynamic Wavelength Grouping for Quality of Service in Optical Packet Switching[J]. IEEE Access, 2021, 9(1): 60946-60959.

[16] Duro J, Petit S, Gómez M E, et al. Segment Switching: A New Switching Strategy for Optical HPC Networks[J]. IEEE Access, 2021, 9(1): 43095-43106.

[17] Cheng J, Yang S H, Wang C Y, et al. On Efficient Constructions of Optical Priority Queues[J]. IEEE Transactions on Communications, 2022, 70(3): 1861-1874.

[18] Parane K, Prasad B M P, Talawar B. Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA[C]// 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2019: 1-5.

[19] Shafiei F, Sattari-Naeini V. Development of an Adaptive Multipath Routing Algorithm by Examining the Congestion and Channel Fault of One-Hop Nodes in Network-on-Chip[C]//2020 8th International Conference on Computer and Knowledge Engineering (ICCKE). IEEE, 2020: 231-236.

[20] Kelley J, Forencich A, Papen G C, et al. Characterization of Burst-Mode Links for Optical Circuit Switching[J]. Journal of Lightwave Technology, 2022, 40(9): 2823-2829.

[21] Forencich A, Kamchevska V, Dupuis N, et al. A Dynamically-Reconfigurable Burst-Mode Link Using a Nanosecond Photonic Switch[J]. Journal of Lightwave Technology, 2020, 38(6): 1330-1340.

[22] Truong T N, Takano R. Hybrid Electrical/Optical Switch Architectures for Training Distributed Deep Learning in Large-Scale[J]. IEICE Transactions on Information and Systems, 2021, 104(8): 1332-1339.

[23] Shen Y, Wang W, Liu T, et al. Energy-efficient Scaling of Active Electrical/Optical Switches in Hybrid Packet/Circuit Switched Data Center Networks[C]//2021 19th International Conference on Optical Communications and Networks (ICOCN). IEEE, 2021: 1-3.

[24] Minakhmetov A, Ware C, Iannone L. Hybrid and optical packet switching supporting different service classes in data center network[J]. Photonic Network Communications, 2020, 40(1): 293-302.

[25] Andreades P and Zervas G.Parallel Modular Scheduler Design for Clos Switches in Optical Data Center Networks[J]. Journal of Lightwave Technology, 2020, 38(13): 3506-3518.

[26] Shao E, Tan G M, Wang Z, et al. A New Optoelectronic Hybrid Network Based on Scheduling Optimization of Optical Links[J]. IEEE Transactions on Computers, 2021, 70(6): 863-876.

[27] Ujalambkar D, Chowdhary G V. Congestion Control in Optical Burst Switching Networks Using Differential Evolution Optimization[C]// 2019 ICICC Advances in Intelligent Systems and Computing(ICICC). 2019: 59-66.

[28] ZHAO L and SHI P. A universal method for constructing n-port reconfigurable non-blocking optical switches on a silicon chip[J], IEEE Access, 2022, 10(1): 1850-1859.

[29] Wang C, Hai H and Wei L, et al. Early Warning Method for Coal and Gas Outburst Prediction Based on Indexes of Deep Learning Model and Statistical Model[J], Frontiers in Earth Science, 2022, 10(1): 187-194.

[30] LI M C, TSENG T M, TALA M, et al. Maximizing the communication parallelism for wavelength-routed optical networks-on-chips[C]//2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2020: 109-114.

[31] Peng H W, Huang S Y, Geng T, et al. Accelerating Transformer-based Deep Learning Models on FPGAs using Column Balanced Block Pruning[C]//2021 22nd International Symposium on Quality Electronic Design (ISQED). IEEE, 2021: 142-148.

[32] LU Y S, YU S J, CHANG Y W. Topological structure and physical layout codesign for wavelength-routed optical networks-on-chip[C]//2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020: 1-6.

[33] ARULANANTH T S, BASKAR M, UDHAYA S, et al. Evaluation of low power consumption network on chip routing architecture[J]. Microprocessors and Microsystems, 2021, 82(1): 1038-1044.

[34] ASADINIA S, MEHRABI M, YAGHOUBI E. Surix: non-blocking and low insertion loss micro-ring resonator-based optical router for photonic network on chip[J]. The Journal of Supercomputing, 2021, 77(1): 4438-4460.

[35] SADAGHIANI A K and GHANBARI M. An optimized hardware design for high speed 2D-DCT processor based on modified Loeffler architecture[C]//2019 27th Iranian Conference on Electrical Engineering (ICEE). 2019: 1476-1480.

[36] 苑乔,张华健,朱进宇等.基于包交换技术的可重构片上网络混合路由器设计[J].微电子学与计算机,2020,37(3):49-54.

[37] Esf A, Majj B, Mm A, et al. An Efficient NoC Router by Optimal Management of Buffer Read and Write Mechanism[J]. Microprocessors and Microsystems, 2022, 10(89): 104-115.

[38] Patil T, Sandi A. Design and implementation of asynchronous NOC architecture with buffer-less router[J]. Materials Today: Proceedings, 2022, 3(49): 756–763.

[39] Li Y, Louri A, Karanth A. SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-Based Accelerator With Photonic Interconnects for CNN Inference. IEEE Transactions on Parallel and Distributed Systems[J]. 2022, 33(10): 2332-2345.

[40] Liu Y Y, Zhang J X, Feng J, et al. A Reliability Concern on Photonic Neural Networks[C]// 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2022: 1059-1064.

[41] Han J H, Liu H, Wang M Y, et al. ERA-LSTM: An Efficient ReRAM-Based Architecture for Long Short-Term Memory[J]. IEEE Transactions on Parallel and Distributed Systems, 2020, 31(6): 1328-1342.

[42] YAN H, XIE Y, YANG X, et al. A novel algorithm for reducing the power loss of routing paths in ONoCs[C]//2020 International Conference on Wireless Communications and Signal Processing (WCSP). 2020, 11(11): 325-330.

[43] YAHYA M R, WU N, ALI Z A, et al. Optical versus electrical: performance evaluation of network on-chip topologies for UWASN manycore processors[J].Wireless Personal Communications, 2021, 116(2): 963-991.

[44] Zhu S Y, Zhou C Q, Wang Y J. Highly Efficient Multicast over Surface Wave in Hybrid Wireless-Optical On-Chip Networks for IoT HPC[J]. Wireless Communications and Mobile Computing, 2022, 38(2): 289-300.

[45] YANG Y, CHEN K, GU H X, et al. TAONoC: A regular passive optical network-on-chip architecture based on comb switches[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(4): 954-963.

[46] ZHENG Z D, Li M C, TSENG T M, et al. Light: a scalable and efficient wavelength-routed optical networks-on-chip topology[C]//2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC). 2021: 568-573.

[47] JIN K, DONG D, LL C, et al. DancerFly: an order-aware network-on-chip router on-the-fly mitigating multi-path packet reordering[J]. International Journal of Parallel Programming, 2020, 48(2): 128-134.

[48] YANG Y, SU Y, LIU B, et al. An n-port universal multimode optical router supporting mode-division multiplexing[J]. Micromachines. 2021, 12(12): 1438-1442.

[49] Roodsari M S, Totonchi H and Navabi Z. n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator[C]//2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2021: 206-211.

[50] Li S J. Design of Handwritten Digit Intelligent Recognition System Based on FPGA Architecture[J].China Computer&communication, 2021, 33(23): 95-97.

中图分类号:

 TN492    

开放日期:

 2024-06-19    

无标题文档

   建议浏览器: 谷歌 火狐 360请用极速模式,双核浏览器请用极速模式