氧化镓(Ga₂O₃)是一种新兴的宽禁带半导体材料，其禁带宽度为4.6-4.9 eV，临界场强高达8 MV/cm，且其在耐高压、高频、抗辐射方面的能力均优于已经广泛投入商用的GaN，SiC材料。因为Ga₂O₃材料在材料性能以及晶圆制备成本上的优势，其在信号基站、日盲探测器、雷达、射频模块、功率器件等领域有着广阔的应用前景。目前Ga₂O₃材料存在的主要问题是难以形成稳定的P型掺杂，因此制备的MOSFET器件大都是N型掺杂的无结型器件。无结型MOSFET一般都是耗尽型器件，不适合应用于功率器件领域。针对上述问题，本文设计了一种具有β-Ga₂O₃/4H-SiC异质结结构的纵向双扩散MOSFET（VDMOS），使用Sentaurus TCAD仿真软件建立了β-Ga₂O₃的材料参数和物理模型，随后搭建了器件结构并进行了电学特性的仿真。基于初始器件结构，通过调节器件的主要结构参数，对器件的电学性能进行了优化，得到了器件性能最优时的主要结构参数。然后考虑到实际器件制备过程中的环境因素以及在工艺过程中可能引入的陷阱和缺陷，添加了热力学模型和陷阱模型，模拟了不同环境因素和不同陷阱对器件性能的影响。具体所作工作如下：

（1）首先通过查阅β-Ga₂O₃相关文献，总结了前人的研究和工作中提出的物理模型和实验数据，并在Sentaurus TCAD仿真软件中建立了较为完整的β-Ga₂O₃材料的仿真模型。基于建立的仿真模型，在软件中模拟搭建了β-Ga₂O₃/4H-SiC VDMOS的器件结构，仿真了初始结构的输出特性、转移特性和击穿特性。随后基于初始结构，通过改变器件的结构参数和材料参数，研究了其对电学性能的影响。通过对器件主要结构参数的优化，优化了器件的阈值电压、比导通电阻、输出电流、击穿电压和功率品质因数(PFOM)，得到了β-Ga₂O₃/4H-SiC VDMOS性能取得最优值时器件的结构参数。优化后的阈值电压为1.62 V，饱和电流为49.51 mA/mm，比导通电阻为5.47 mΩ·cm²，功率品质因数高达617 MW/cm²，击穿电压为1838 V。通过与传统无结器件的性能对比发现，本研究设计的β-Ga₂O₃/4H-SiC异质结VDMOS具有更低的比导通电阻和更高的击穿电压。该结构在实现增强型的同时具有更加优异的PFOM值，更加适合于功率器件。

（2）随后考虑到在实际器件的制备过程中存在的非理想因素会对器件性能造成一定的影响，在Sentaurus TCAD中添加了热力学模型和陷阱模型，模拟了非理想效应对β-Ga₂O₃/4H-SiC VDMOS性能的影响。首先考虑了器件的自热效应，模拟了在不同环境温度和热阻下，器件的性能变化和内部温度分布情况。模拟结果表明，外界温度的升高和热阻的增大，都会引起器件内部温度升高，从而导致器件性能的退化。同时器件内部温度分布图显示器件内部温度最高点在外延层中，温度沿外延层向源漏极方向逐渐降低。然后分析了器件制备过程中栅介质/半导体界面处可能存在的陷阱类型，分别研究了在添加界面态、栅介质层固定电荷以及近界面陷阱后器件性能的变化。模拟结果表明，为了使界面处陷阱对器件性能的影响降到最低，在器件制备时，应尽可能地将栅介质层固定电荷密度控制在1×10¹¹ cm^-2以下，近界面陷阱浓度控制在5×10¹⁸ cm^-3以下，界面陷阱密度控制在1×10¹³ cm^-2以下。最后分别研究了β-Ga₂O₃和4H-SiC中体缺陷对于器件性能的影响，模拟结果表明，为了降低体缺陷对于器件性能的影响，在器件制备时最好将β-Ga₂O₃中体缺陷浓度控制在1×10¹³ cm^-3以下，将4H-SiC中体缺陷浓度控制在1×10¹⁶ cm^-3以下。

上述结论表明，本研究设计的β-Ga₂O₃/4H-SiC VDMOS为实现高性能增强型β-Ga₂O₃功率器件提供了一种可行的设计思路，同时为以后的器件制备和性能优化提供了参考方案。

Gallium oxide (Ga₂O₃) is a new semiconductor material with a wide band gap of 4.6-4.9 eV, and its critical breakdown field strength is as high as 8 MV/cm, and it is superior to GaN and SiC which have been widely put into commercial use in the aspects of high voltage resistance, high frequency resistance and radiation resistance. Because of its advantages in material properties and wafer preparation cost, Ga₂O₃ has broad application prospects in signal base stations, solar blind detectors, radars, radio frequency modules, power devices and other fields. At present, the main problem of Ga₂O₃ material is that it is difficult to form stable P-type doping, so most of the prepared MOSFET devices are N-type doped junctionless devices. Junctionless MOSFETs are generally depletion mode devices, which are not suitable for power device field. In order to solve the above problems, we design a vertical double diffusion MOSFET (VDMOS) with β-Ga₂O₃/4H-SiC heterojunction structure, establishes the material parameters and physical model of β-Ga₂O₃ by using Sentaurus TCAD simulation software, and then builds the device structure and simulates the electrical characteristics. Based on the initial device structure, the electrical properties of the device are optimized by adjusting the main structural parameters of the device, and the main structural parameters when the device performance is optimal are obtained. Then, considering the environmental factors in the actual device preparation process and the traps and defects that may be introduced in the process, we add thermodynamic models and trap models to simulate the effects of different environmental factors and different traps on the device performance. The specific works are as follows:

(1) Firstly, we summarized the physical models and experimental datas put forward by predecessors' researchs and works by consulting the relevant literature of β-Ga₂O₃, and established the relatively complete simulation models of β-Ga₂O₃ in Sentaurus TCAD simulation software. Based on the established simulation models, the device structure of β-Ga₂O₃/4H-SiC VDMOS is simulated in the software, and the output characteristic，transfer characteristic and breakdown characteristic of the initial structure are simulated. Then, based on the initial structure, the influence of changing the structural and material parameters of the device on its electrical performance was studied. By optimizing the main structural parameters of device, the threshold voltage, specific on-resistance, saturation current, breakdown voltage and power figure of merit (PFOM) of the device are optimized, and the structural parameters of the device when the performance of β-Ga₂O₃/4H-SiC VDMOS reaches the optimal value are obtained. The optimized threshold voltage is 1.62 V, the saturation current is 49.51 mA/mm, the Specific on-resistance is 5.47 mΩ·cm², the power quality factor is as high as 617 MW/cm², and the breakdown voltage is 1838 V. Compared with the traditional junction-free devices, it is found that the β-Ga₂O₃/4H-SiC heterojunction VDMOS designed in this study has lower specific on-resistance and higher breakdown voltage. This structure has better PFOM value while realizing enhancement, and is more suitable for power devices.

(2) Then, considering that the non-ideal factors in the actual device preparation process will have a certain impact on the device performance, adding the thermodynamic models and trap models in Sentaurus TCAD to simulate the impact of non-ideal effects on the  performance of β-Ga₂O₃/4H-SiC VDMOS. Firstly, we considered the self-heating effect of the device, and the performance change and internal temperature distribution of the device are simulated under different environmental temperatures and thermal resistances. The simulation results show that the increase of external temperature and thermal resistance will cause the increase of the internal temperature of the device, which will lead to the degradation of the device performance. The internal temperature distribution diagram of the device shows that the highest temperature in the device is in the epitaxial layer, and the temperature gradually decreases along the epitaxial layer towards the source and drain. Then, we analyzed the possible trap types at the gate dielectric/semiconductor interface during device preparation, and the changes of device performance after adding interface state, fixed charge of gate dielectric layer and near-interface traps are studied respectively. The simulation results show that in order to minimize the influence of traps at interface on the device performance, the fixed charge density of gate dielectric layer should be controlled below 1×10¹¹ cm^-2, the near-interface trap concentration should be controlled below 5×10¹⁸ cm^-3 and the interface trap density should be controlled below 1×10¹³ cm^-2. Finally, the effects of bulk defects in β-Ga₂O₃ and 4H-SiC on the device performance are studied respectively. The simulation results show that in order to reduce the influence of bulk defects on the device performance, it is best to control the bulk defects concentration in β-Ga₂O₃ below 1×10¹³ cm^-3 and in 4H-SiC below 1×10¹⁶ cm^-3 during device preparation.

The above conclusions show that the β-Ga₂O₃/4H-SiC VDMOS designed in this study provides a feasible design idea for realizing high-performance enhanced β-Ga₂O₃ power devices, and also provides a reference scheme for device preparation and performance optimization in the future.

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