电荷泵锁相环具有宽输出范围、快锁定时间、高分辨率和低成本的优点，被广泛应用于无线通信、数据转换器和高速数字电路系统中。但电荷泵锁相环内部各模块的噪声会直接叠加到输出端，使得输出信号产生抖动。因此，设计一款低相位噪声电荷泵锁相环具有重要的理论意义及应用价值。

通过分析电荷泵锁相环的基本结构和工作原理建立各模块的数学模型，在此基础上推导电荷泵锁相环的传递函数，并分析其环路稳定性。根据性能指标要求确定环路参数，并通过系统级仿真验证了参数设计的合理性。通过分析各模块噪声来源并推导噪声传递函数，得出了锁相环整体的噪声传输特性，并针对各模块的噪声传输特性分别提出了噪声抑制方案。针对鉴频鉴相器存在鉴相死区导致鉴相范围受限的问题，设计了差分鉴频鉴相器电路，通过合理设置复位脉冲宽度抑制了其“死区效应”；针对传统电荷泵存在非理想效应导致充放电电流匹配度较差的问题，设计了一种全差分电荷泵电路，采用低压共源共栅结构以提高电流源的输出阻抗，采用两组N型MOS管作为电荷泵开关管，消除了不同类型开关管之间存在的电流失配，并确保用作电流源的MOS管持续导通，有效抑制了传统电荷泵固有的非理想效应，提高了充放电电流的匹配度；针对控制电压易受电源波动影响的问题，设计了一种专用延迟单元偏置电路，为压控振荡器中的延迟单元提供不随电源电压变化的偏置电压；最终设计了一款参考频率为25MHz，输出频率为400MHz的低相位噪声电荷泵锁相环。

基于SMIC 0.18μm CMOS工艺，采用Spectre工具对电荷泵锁相环整体电路进行仿真。仿真结果表明，输出频率为400MHz时，电荷泵锁相环的锁定时间为3.5μs，电源电压为1.8V，功耗为6.24mW，输出信号抖动小于9ps，1MHz频率偏移处的相位噪声约为-104.15dBc/Hz。完成了电荷泵锁相环版图设计，并通过了DRC、LVS验证。提取版图寄生参数并完成了后仿，仿真结果验证了设计方案的可行性。

Charge Pump Phase Locked Loop (CPPLL) has the advantages of wide output frequency range, fast locking time, high resolution and low cost, and is widely used in wireless communication, data converter and high-speed digital circuit system. However, the noise of each module in CPPLL is directly coupled to the output, which causing jitter in the output clock signal. Therefore, the design of a CPPLL with low phase noise has important theoretical significance and engineering application value.

Through analyzing the basic structure and working principle of CPPLL, mathematical models of each module are established. On this basis, the transfer function of CPPLL is deduced. Besides, its loop stability are analyzed. According to the performance requirements, loop parameters are determined, and the rationality of loop parameters design is verified by system-level simulation. By analyzing the noise sources of each module and deriving the noise transfer functions, the overall noise transmission characteristic of the CPPLL is obtained, and the noise suppression scheme of each module is proposed for the noise transmission characteristics. Aiming at the problem that phase frequency detector has "dead zone effect" which limits the phase detection range, a differential phase frequency detector circuit is designed, and its "dead zone effect" is eleminated by setting the reset pulse width reasonably; Aiming at the problem that traditional charge pump which has mismatch between charge and discharge currents caused by the non-ideal effect, a fully differential charge pump circuit is designed, and the low voltage common source current mirror is used to improve the current replication precision. Two sets of NMOS are used as charge pump switches, the mismatch between different types of switches is suppressed, the continuous conduction of MOS as current source is assured, the non-ideal effects of traditional charge pump are effectively suppressed, and the matching degree of charge and discharge current is effectively improved; Aiming at the problem that control voltage is susceptible to power fluctuation, a dedicated delay unit bias circuit is designed to provide bias voltage which does not change with the power voltage to the delay unit. Based on D filp-flop triggered by edge, a basic 2 frequency divider circuit is designed, and a 16 frequency divider is realized by cascading the basic 2 frequency dividers; Finally, a low phase noise CPPLL with a reference frequency of 25 MHz and an output frequency of 400 MHz is designed.

Based on SMIC 0.18 μm CMOS process，Spectre simulation tool is used to simulate and analyze the overall circuit. Simulation results show that when the output frequency is 400MHz, the lock-in time is 3.5μs, the power consumption at 1.8V supply is 6.24mW, the jitter of output signal is less than 9ps, and the phase noise at 1MHz frequency deviation is -104.15dBc/Hz. The overall layout of the chip is completed, and the DRC and LVS verification is passed. The simulation results verify the correctness of the theoretical analysis and the feasibility of the design scheme.

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