便携式电子产品的普及对电源管理芯片的低成本、低功耗提出了更高要求。为此，本文在对双极、CMOS及BCD工艺进行深入分析的基础上，提出了一种可兼容CMOS工艺且适合功率集成电路的CD工艺，并对基于所提出CD工艺的DC-DC变换器的关键电路进行研究，对推出低成本、低功耗的DC-DC电源管理芯片具有重要参考价值。 通过对CMOS工艺下，高/低压与功率器件的工艺兼容性及隔离和PN结终端处理技术进行研究，在标准双阱CMOS工艺基础上增加一次深N阱注入，实现了高压CMOS与功率LDMOS集成，进而得到一种满足课题需求的低成本CD工艺。通过对BUCK DC-DC变换器工作原理与控制方式进行分析，设计出基于CD工艺的DC-DC变换器芯片系统结构。利用NMOS与PMOS管阈值电压随温度线性变化的原理通过加权求和电路抵消温度系数，设计出一种具有理论上极低温度系数且大小可调的全CMOS结构基准电压源，使面积与功耗比常规带隙基准源有所减小。利用NMOS管亚阈值I-V特性感应温度变化设计出带热滞回功能的全CMOS结构过热保护电路，同样解决了CMOS电路中使用三极管的弊端。设计的电流检测电路利用比例电流源技术，使检测损耗得以降低、效率得以提高。此外，芯片还设计了过流与欠压等保护电路，及频率可变的输出短路保护功能，以保证用户系统安全。在对各关键模块与整体应用电路使用HSPICE软件仿真验证之后，采用华润上华0.5um工艺规则于Cadence Virtuoso平台对芯片进行了版图设计，并通过DRC与LVS检查，验证了版图设计的正确性。 所设计的CD工艺不仅复杂度比BCD工艺大幅降低，而且缩小了芯片面积，从而实现了降低成本与功耗的目的。基于CD工艺设计的DC-DC变换器芯片经仿真验证表明了理论的正确性与方案的可行性。该芯片只需外接少量元件，就可构成高性能、低成本的DC-DC变换器，并广泛应用于各种便携式电子产品。

The popularity of portable electronic products makes higher requests to power management chips on low cost and low power consumption. Therefore, based on thorough analysis of the Bipolar, CMOS and BCD process, a CD process, which is compatible with CMOS process and suitable for power ICs, is put forward in the thesis. And researches on the key circuits of the DC-DC converter chip implemented with the proposed CD process are also carried out, which has great reference value for the proposal of the low cost and low power consumption DC-DC power management chips. Through the researches on the process compatibility and isolation & PN junction terminal treatment technology between high/low-voltage and power devices under the CMOS process, a low-cost CD process is proposed by adding a deep N-well injection step on the basis of standard double-well CMOS process to realize the integration of high-voltage CMOS and power LDMOS devices, which can meet the demands of current subject. And the system architecture of the DC-DC converter chip implemented with the proposed CD process is worked out through the analysis of the working principle and control mode of the BUCK DC-DC converter. Besides, a voltage-adjustable full-CMOS-structured voltage reference with theoretically extremely low temperature coefficient is designed by adopting weighted summation circuit to counteract the temperature coefficient, which is based on the principle that the threshold voltage of NMOS and PMOS varies linearly with the temperature. As a result, the chip area and power consumption are reduced comparing with that of original bandgap reference. Additionally, a full-CMOS-structured OTP circuit with thermal hysteresis function is proposed by making use of the NMOS sub-threshold I-V characteristic to induce temperature variation, which can also solve the problems caused by bipolar transistors used in the CMOS circuit. Moreover, the designed current detection circuit takes advantage of the proportional current source technology to reduce detection loss and improve efficiency. Furthermore, there are over-current and under-voltage protection circuits in the chip, as well as the frequency-variable output short-circuit protection function to ensure the safety of the user system. After the simulation and verification of each key module and the application circuits by HSPICE, the chip layout with CSMC 0.5um design rules is designed on the Cadence Virtuoso platform. And the DRC and LVS check are both passed to prove the correctness of the layout. Compared with BCD process, the proposed CD process has not only drastically reduced complexity, but also considerably diminished chip area. As a result, the purpose of reducing cost and power consumption is achieved. And the simulation results show that the design of the DC-DC converter chip implemented with the proposed CD process is correct in theory and feasible in program. As long as a small amount of components are externally connected, the chip can easily constitute a DC-DC converter with high performance and low cost and be widely used in different kinds of portable electronic products.