霍尔传感器技术在现代信息技术中起着重要作用，而霍尔元件作为其重要组成部分，在工艺误差、外界温度变化及机械应力下，产生的失调电压严重影响霍尔传感器对磁场的检测精度。低噪声及高灵敏度霍尔传感器可实现低磁场强度下的可靠工作，增加芯片的应用范围。因此，研究并设计一款低失调电压、低噪声、高灵敏度的霍尔传感器芯片具有重要理论意义及工程应用价值。 通过对霍尔元件产生失调电压的来源进行研究，得出了十字形霍尔元件结构相比于长方形霍尔元件结构具有面积小、失调电压低等优势，提出了采用十字形结构进行霍尔元件版图设计的方案。为了进一步消除霍尔元件产生的失调电压，提出了采用正交旋转电流法的方案，实现霍尔电压及失调电压的分离，并通过跟踪-保持技术将分离后的失调电压消除。通过对霍尔元件外围电路产生额外失调电压及噪声来源的研究，提出了采用调制-解调原理控制的斩波放大技术，将霍尔电压转换到低频段，而失调电压及噪声分散到高频段，实现霍尔电压与失调电压、噪声信号的频域分离，并通过低通滤波等方案完成失调电压及噪声消除。通过对开关型霍尔传感器灵敏度原理进行分析，推导得出灵敏度与比较器滞回区间及供电电压的关系式，提出了实现双极型霍尔传感器芯片高灵敏度的设计方案。同时，对芯片内部的基准、LDO、仪用放大器、振荡器、时钟处理、复位及滞回比较器等模块电路及关键元件参数进行设计，完成了一款低失调电压、低噪声、高灵敏度CMOS双极型霍尔传感器芯片的设计。基于CSMC_0.35μm仿真库文件，结合Hspice软件对整体电路进行了仿真分析，结果验证了理论分析及设计方法的可行性。 采用Cadence软件实现了整体电路的版图设计，通过了DRC、LVS验证，提取参数后实现了后仿验证，并对流片后芯片进行测试，结果验证了所设计芯片及版图的可行性。

Hall sensor technology plays an important role in modern information technology, However, under the process error, changing external temperature and mechanical stress, the seriously offset voltage of the Hall plate which is a important part of the Hall sensor affects the detection accuracy of the Hall sensor. The low noise and high sensitivity Hall sensor can work reliably at low magnetic field strength, which increases the range of applications of the chip. There, the study of a low offset voltage, low noise, high sensitivity Hall sensor chip with high power factor has important theoretical significance and engineering application value. By studying the source of the offset voltage generated by the Hall plate, it is concluded that the cross-shaped Hall plate structure has the advantages of small area and low offset voltage compared with the rectangular Hall plate structure. A scheme for designing the layout of Hall plate using a cross-shaped structure is proposed. In order to further eliminate the offset voltage generated by the Hall plate, a quadrature rotating current method is proposed to separate the Hall voltage and the offset voltage, and the separated offset voltage is eliminated by the tracking-holding technique. By studying the extra offset voltage and noise, a chopper amplification technique controlled by the modulation-demodulation principle is proposed. The ultimate goal of this technology convert the Hall voltage to the low frequency band while the offset voltage and the noise are dispersed to a high frequency band. The frequency domain separation is achieved, and the offset voltage and noise are eliminated completed by a low-pass filtering scheme. By analyzing the sensitivity principle of the switch Hall sensor, the expressions of the sensitivity and the hysteresis interval of the comparator are derived. The high sensitivity method of the bipolar Hall sensor chip is proposed. At the same time, the internal circuit of the chip, such as reference, LDO, instrumentation amplifier, oscillator, clock processing, reset and hysteresis comparator circuit are designed. Moreover, A low offset voltage, low noise, high sensitivity CMOS bipolar Hall sensor chip is designed. Based on the CSMC_0.35μm simulation library file, combined with Hspice software, the whole circuit was simulated and analyzed. The simulation results show that the feasibility of the designed chip. The Cadence software was used to realize the layout design of the whole circuit. After the DRC and LVS verification, the parameters were extracted and the post-simulation verification was implemented. The results show that the feasibility of the designed chip and layout.